1. Field of the Invention
The present invention pertains to memories and memory testing. More particularly, this invention relates to direct access testing of embedded memory.
2. Background
Continual advances in processor technology have led to continual increases in the functionality provided in a single processor chip. One example of such functionality is on-chip memories, often referred to as cache memories. On-chip cache memories provide storage of data and/or instructions as well as various other control and/or address information for use by the execution unit(s) and other internal logic of the processor. These on-chip cache memories are typically very fast memories, with the combination of their speed as well as their close physical locality to the execution unit(s) and other internal logic leading to fast memory accesses for the information stored in these memories.
However, the fabrication of memories does not produce perfect results and, therefore, processors will occasionally be fabricated which have faulty memories. The faults may be complete failure of the memory cells, failure of particular cells, failure only under certain circumstances, etc. Therefore, given that processors with such faulty memories may be fabricated, it would be beneficial to provide a way to test the embedded memories to verify their performance. Unfortunately, given the embedded nature of these memories, it is typically not possible to directly access them from external to the processor, thereby making testing very difficult.
An additional concern in testing embedded memory is the amount of chip "real estate" which is taken up by the testing logic. Once operation of the embedded memory has been verified the testing of the embedded memory is typically not repeated. Therefore, it would be preferable to reduce the amount of chip real estate used for logic dedicated solely to the testing of the embedded memory.
One solution to testing embedded memories is to generate a software test program which, when executed by the execution unit(s) of the processor, requires the use of the embedded memories. By carefully selecting the instructions and data for testing, portions of the embedded memories can be checked and performance verified. However, this solution requires very careful planning by the test program designer and a thorough knowledge of the overall processor architecture in order for the designer to know how the instructions will be executed and information stored in the memories. Furthermore, this solution makes it very difficult to exactly identify which particular memory cell malfunctioned in response to which particular instruction.
Thus, a need exists for improved testing of embedded memories.